An integrated circuit (“IC”) is a device (e.g., a semiconductor device) that includes many electronic components, such as transistors, resistors, diodes, etc. These components are often interconnected to form multiple circuit components, such as gates, cells, memory units, arithmetic units, controllers, decoders, etc. An IC includes multiple layers of wiring that interconnect its electronic and circuit components. Traditionally, IC's use preferred direction (“PD”) wiring models, which specify a preferred wiring direction for each of their wiring layers. In preferred direction wiring models, the preferred direction typically alternates between successive wiring layers. One example of a PD wiring model is the PD Manhattan wiring model, which specifies alternating layers of preferred-direction horizontal and vertical wiring.
Design engineers design IC's by transforming logical or circuit descriptions of the IC's into geometric descriptions, called layouts. IC layouts typically include (1) circuit modules (i.e., geometric representations of electronic or circuit IC components) with pins, and (2) interconnect lines (i.e., geometric representations of wiring) that connect the pins of the circuit modules. A net is typically defined as a collection of pins that need to be connected. A list of all or some of the nets in a layout is referred to as a net list.
To create layouts, design engineers typically use electronic design automation (“EDA”) applications. These applications provide sets of computer-based tools for creating, editing, and analyzing IC design layouts. One EDA tool is a router that defines routes for interconnect lines that typically connect the pins of nets. While some commercial routers today might allow an occasional diagonal jog, these routers do not typically explore diagonal routing directions consistently when they are specifying the routing geometries of the interconnect lines. This, in turn, increases the total wirelength (i.e., total length of interconnect lines) needed to connect the nets in the layout.
There are certain techniques during manufacturing that require certain geometries have a minimum length. FIG. 1 conceptually illustrates a portion of an IC layout design 100 consisting of a pin 105, a via 110 (vias are further described in Section I below), an interconnect line 115 connecting the pin 105 and the via 110, and another interconnect line 120 in the same layer connecting the via 110 to other circuit geometries. Ideally, after the manufacturing process, the corresponding fabricated portion of the IC must look like a single piece of metal 125 with the same outline as the original IC layout design 100.
In order to generate a pattern such as 125 on an IC wafer, some IC fabrication processes use a photomask and a visible or ultraviolet light source. The wafer surface is covered by a layer of either electrically insulating or electrically conductive material. This material is then coated with a photosensitive resist. The light source is then used to project the image on the photomask onto the wafer. The resist is then developed in a developer solution after its exposure to light to produce patterns that define which areas of the wafer are exposed for material deposition or removal.
In practice, in order to make the fabricated pattern 125 to look as close as the original IC layout design 100, certain techniques such as Optical Proximity Correction (OPC) are utilized that would require some geometries on the IC surface to have a minimum length. For instance, the OPC technique improves the IC yield by applying systematic changes to the photomask geometries to compensate for nonlinear distortions caused by optical diffraction and resist process effects. OPC makes small changes to the IC layout that anticipate the distortion. Small shapes may be added or subtracted from corners to produce corners in the fabricated IC that are closer to the ideal layout. As a result, certain edges in the IC design layout have to have a minimum length for OPC or similar processes to work properly. There is, therefore, a need in the art for a technique to ensure a minimum length for certain edges and interconnects lines during the routing process.